參數(shù)資料
型號： M3062AFCVGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 53/104頁
文件大小： 1313K
代理商： M3062AFCVGP
5. Electrical Characteristics
Rev.2.41
Jan 10, 2006
Page 50 of 96
REJ03B0001-0241
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr =
20 to 85°C / 40 to 85°C unless otherwise specified)
NOTES:
1. The condition is VCC1=VCC2=3.0 to 5.0V.
NOTES:
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
n is “2” for 2-wait setting, “3” for 3-wait setting.
Table 5.13
External Clock Input (XIN input) (1)
Symbol
Parameter
Standard
Unit
Min.
Max.
tc
External Clock Input Cycle Time
62.5
ns
tw(H)
External Clock Input HIGH Pulse Width
25
ns
tw(L)
External Clock Input LOW Pulse Width
25
ns
tr
External Clock Rise Time
15
ns
tf
External Clock Fall Time
15
ns
Table 5.14
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Unit
Min.
Max.
tac1(RD-DB)
Data Input Access Time (for setting with no wait)
ns
tac2(RD-DB)
Data Input Access Time (for setting with wait)
ns
tac3(RD-DB)
Data Input Access Time (when accessing multiplex bus area)
ns
tsu(DB-RD)
Data Input Setup Time
40
ns
tsu(RDY-BCLK)
RDY Input Setup Time
30
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
40
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
ns
0.5x10
9
fBCLK
()
------------------------45 ns
[]
–
n0.5
–
()x10
9
fBCLK
()
-------------------------------------45 ns
[]
–
n0.5
–
()x10
9
fBCLK
()
-------------------------------------45 ns
[]
–
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