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| 型號(hào)： | M30624FGMFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 137/274頁(yè) |
| 文件大?。?/td> | 3495K |
| 代理商： | M30624FGMFP |
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Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
137
An attempt to read Port P7
1
(SCL) results in getting the terminal’s level regardless of the content of the
port direction register. The initial value of SDA transmission output in this mode goes to the value set in
port P7
0
. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and
of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-
detection interrupt, and acknowledgment detection interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P7
0
) is detected with the SCL terminal (P7
1
) staying “H”. The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P7
0
) is detected with the SCL
terminal (P7
1
) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
start condition detection, and set to “0” by the stop condition detection.
The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal
level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment
detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went
to “L” at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor
select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection.
Bit 1 of the UART2 special mode register (0377
16
) is used as the arbitration loss detecting flag control bit.
Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal
data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2 reception
buffer register (037F
16
), and “1” is set in this flag when nonconformity is detected. Use the arbitration lost
detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When
setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost
detecting flag is set to “1” at the falling edge of the 9th transmission clock.
If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after complet-
ing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting
this bit to “1” goes the P7
1
data register to “0” in synchronization with the SCL terminal level going to “L”.
Figure 1.16.27 shows the functional block diagram for I
2
C mode. Setting “1” in the I
2
C mode select bit
(IICM) causes ports P7
0
, P7
1
, and P7
2
to work as data transmission-reception terminal SDA, clock input-
output terminal SCL, and port P7
2
respectively. A delay circuit is added to the SDA transmission output,
so the SDA output changes after SCL fully goes to “L”. The SDA digital delay select bit (bit 7 at address
0377
16
) can be used to select between analog delay and digital delay. When digital delay is selected, the
amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode
register 3 (at address 0375
16
). Delay circuit select conditions are shown in Table 1.16.10.
Table 1.16.10. Delay circuit select conditions
Digital delay is
selected
001
to
111
000
(000)
1
0
1
1
1
Analog delay is
selected
No delay
0
0
(000)
IICM
SDDS
DL
Register value
Contents
When digital delay is selected, no analog delay is added. Only
digital delay is effective.
When DL is set to “000”, analog delay is selected no matter what
value is set in SDDS.
When SDDS is set to “0”, DL is initialized, so that DL =“000”.
When IICM = “0”, no delay circuit is selected. When IICM = “0”,
however, always make sure SDDS = “0”.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30624FGMFP#D3 | 功能描述:IC M16C MCU FLASH 256K 100-QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:M16C™ M16C/60 標(biāo)準(zhǔn)包裝:160 系列:S08 核心處理器:S08 芯體尺寸:8-位 速度:40MHz 連通性:I²C，LIN，SCI，SPI 外圍設(shè)備:LCD，LVD，POR，PWM，WDT 輸入/輸出數(shù):53 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1.9K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 12x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:64-LQFP 包裝:托盤 |
| M30624FGMFP#D5 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-bit M16C CISC 256KB Flash 3.3V 100-Pin PQFP 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT M16C CISC 256KB FLASH 3.3V 100PQFP - Trays |
| M30624FGMFP#U3 | 制造商:Renesas Electronics Corporation 功能描述:16BIT M16C CISC 256KB FLASH 10MHZ 3.3V 100QFP - Trays |
| M30624FGMFP#U5 | 功能描述:MCU 3/5V 256K PB-FREE 100-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:M16C™ M16C/60 標(biāo)準(zhǔn)包裝:160 系列:S08 核心處理器:S08 芯體尺寸:8-位 速度:40MHz 連通性:I²C，LIN，SCI，SPI 外圍設(shè)備:LCD，LVD，POR，PWM，WDT 輸入/輸出數(shù):53 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1.9K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 12x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:64-LQFP 包裝:托盤 |
| M30624FGMGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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