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25
Tentative Specifications REV.A
S
pecifications in this manual are tentative and subject to change.
Memory Space Expansion Functions
Mitsubishi microcomputers
M16C / 62T Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
deveopmen
(3) Expansion mode 2
In expansion mode 2, the data bank register (0000B
16
) goes effective. Figure 1.8.4 shows the data bank
register.
Figure 1.8.4. Data bank register
Data bank register
Symbol
DBR
Address
000B
16
When reset
00
16
Bit name
Description
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
OFS
Offset bit
0: Not offset
1: Offset
BSR
Bank selection bits
0 1 0: Bank 2
1 0 0: Bank 4
1 1 0: Bank 6
0 1 1: Bank 3
1 0 1: Bank 5
1 1 1: Bank 7
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
b5 b4 b3
b5 b4 b3
Microprocessor
mode
AAAAA
SFR area
Internal RAM area
Internal area reserved
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
D0000
16
08000
16
Memory
expansion mode
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
SFR are
a
Internal RAM area
Internal ROM area
Internal area reserved
CS3
(16K bytes)
CS2
(128K bytes)
CS1
(96K bytes)
28000
16
40000
16
04000
16
Expansion mode 2 (memory space = 4M bytes for PM15 = 1, PM14 = 1)
CS0
Addresses from 40000
16
through BFFFF
16
Bank 7 in fetching a program
A bank selected by use of the bank selection
bits in accessing data
Addresses from C0000
16
through FFFFF
16
Bank 7 invariably
Bank number is output to CS3 to CS1
Memory expansion mode:
512K bytes x 7banks +
256K bytes
Microprocessor mode:
512K bytes x 8banks
Type No.
XXXXX
16
YYYYY
16
00FFF
16
M30623M4T-XXXGP
M30622M8T/M8V-XXXFP
M30623M8T/M8V-XXXGP
M30622MCT/MCV-XXXFP
M30623MCT/MCV-XXXGP
F8000
16
013FF
16
F0000
16
017FF
16
E0000
16
Note 1. M30623(80-pin package) is not provided with the
output pin for the chip select signal.
Note 2. The M16C/62T group is not guaranteed to operate
in memory expansion and microprocessor modes.
Note 3. The memory maps in single-chip mode are omitted.
Figure 1.8.5. Memory location and chip select area in expansion mode 2