CPU Rewrite Mode (Flash Memory Version)
196
Mitsubishi microcomputers
M16C / 62N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
End
Start
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Single-chip mode, memory expansion
mode, or boot mode
Set processor mode register (Note 1)
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Transfer CPU rewrite mode control
program to internal RAM
(Boot mode only)
Write “0” to user ROM area select bit (Note 4)
Write “0” to CPU rewrite mode select bit
(Boot mode only)
Set user ROM area select bit to “1”
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)(Note 2)
*1
Program in ROM
Program in RAM
Note 1: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6
at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) = “0” (without internal access wait state)
10.0 MHz or less when wait bit (bit 7 at address 000516) = “1” (with internal access wait state)
Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of
an area other than the internal flash memory. Also only when NMI pin is “H” level.
Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed.
Figure 1.29.2. CPU rewrite mode set/reset flowchart
Figure 1.29.2b. Shifting to the low power dissipation mode flowchart
End
Start
XIN oscillating
Transfer the program to be executed in the low
power dissipation mode, to the internal RAM.
Switch the count source of BCLK.
XIN stop. (Note 2)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Note 1: For flash memory reset bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession.
When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA
transfer will be executed during the interval.
Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably.
Note 3: Make a waiting time for 10
s by software.
In this waiting time, do not access flash memory.
Wait time until the internal circuit stabilizes (10
s)
(Note 3)
Set flash memory reset bit to “0”
Set flash memory reset bit to “1”
(by writing “0” and then “1” in succession)(Note 1)
*1
Program in ROM
Program in RAM
Process of low power dissipation mode
Wait until the XIN has stabilized
Switch the count source of BCLK (Note 2)
Set CPU rewrite mode select bit to “1”
(by writing “0” and then “1” in succession)
Set CPU rewrite mode select bit to “0”