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參數(shù)資料
| 型號(hào)： | M30622MCV-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 51/190頁(yè) |
| 文件大?。?/td> | 2882K |
| 代理商： | M30622MCV-XXXFP |
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141
Mitsubishi microcomputers
M16C / 62T Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
Figure 1.19.27 shows the functional block diagram for IIC mode. Setting “1” in the IIC mode selection bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-
output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,
so the SDA output changes after SCL fully goes to “L”. An attempt to read Port P71 (SCL) results in
getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA
transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision
detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop
condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection
interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL
terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
start condition detection, and set to “0” by the stop condition detection.
In the first place, the control bits related to the IIC bus(simplified IIC bus) interface are explained.
Bit 0 of the UART special mode register (037716) is used as the IIC mode selection bit. Setting “1” in the
IIC mode select bit (bit 0) goes the circuit to achieve the IIC bus interface effective. Table 1.19.9 shows
the relation between the IIC mode select bit and respective control workings. Since this function uses
clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
P70 through P72 conforming to the simplified IIC bus
Selector
I/O
Timer
delay
Noize
Filter
Timer
UART2
Selector
(Port P71 output data latch)
I/O
P70/TxD2/SDA
P71/RxD2/SCL
Reception register
CLK
Internal clock
UART2
External clock
Selector
UART2
I/O
Timer
P72/CLK2
Arbitration
Start condition detection
Stop condition detection
Data bus
Falling edge
detection
D
T
Q
D
T
Q
D
T
Q
NACK
ACK
UART2
R
UART2 transmission/
NACK interrupt
request
UART2 reception/ACK
interrupt request
DMA1 request
9th pulse
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1
IICM=0
Port reading
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
L-synchronous
output enabling bit
S
R Q
Bus busy
IICM=1
IICM=0
Bus collision/start, stop
condition detection
interrupt request
Bus collision
detection
Noize
Filter
Transmission
register
To DMA0, DMA1
Q
Noize
Filter
To DMA0
Note 1: In M30623(80-pin package), P72/CLK2 is not connected to external pin.
Figure 1.19.27. Functional block diagram for IIC mode
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PDF描述 |
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| M30623MCV-XXXGP | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| M30623M8T-XXXGP | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| M30622ECVFP | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30622MC-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY |
| M30622MC-XXXFS | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY |
| M30622MC-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY |
| M30622MEP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30622MEP-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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