參數(shù)資料
型號(hào)： M30622M8A-XXXGP
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 27/40頁(yè)
文件大?。?/td> 3893K
代理商： M30622M8A-XXXGP
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
30
_____
______
________
Table 1.9.4. Operation of RD, WR, and BHE signals
Status of external data bus
RD
BHE
WR
HL
L
LHL
HLH
LH
H
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Data bus width
A0
H
L
HL
L
LHL
L
HL
H / L
LH
H / L
8-bit
(BYTE = “H”)
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
16-bit
(BYTE = “L”)
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRH
WRL
RD
Data bus width
16-bit
(BYTE = “L”)
H
L
H
L
H
L
_____
________
_________
Table 1.9.3. Operation of RD, WRL, and WRH signals
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
_____ ________
______
_____
________
_________
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
_____
______
_______
pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 1.9.3 and 1.9.4 show the operation of these signals.
_____
______
________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “H”
When BYTE pin = “L”
ALE
Address
Data (Note 1)
Address (Note 2)
D0/A0 to D7/A7
A8 to A19
ALE
Address
Data (Note 1)
Address
D0/A1 to D7/A8
A9 to A19
Address
A0
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.9.3. ALE signal and address/data bus
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