Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
136
Item
Specification
Transfer data format
Transfer data 8-bit UART mode
(bit 2 through bit 0 of address 0378
16
= “101
2
”)
One stop bit (bit 4 of address 0378
16
= “0”)
With the direct format chosen
Set parity to “even”
(bit 5 and bit 6 of address 0378
16
= “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D
16
= “0”).
Set transfer format to LSB (bit 7 of address 037C
16
= “0”).
With the inverse format chosen
Set parity to “odd”
(bit 5 and bit 6 of address 0378
16
= “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D
16
= “1”)
Set transfer format to MSB (bit 7 of address 037C
16
= “1”)
With the internal clock chosen (bit 3 of address 0378
16
= “0”) : fi / 16 (n + 1) (Note 1) : fi=f
1
, f
8
, f
32
(Do not set external clock)
Disable the CTS and RTS function (bit 4 of address 037C
16
= “1”)
The sleep mode select function is not available for UART2
Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D
16
= “1”)
Transmission start condition
To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D
16
) = “1”
- Transmit buffer empty flag (bit 1 of address 037D
16
) = “0”
R
eceptio
n start condition
To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D
16
) = “1”
- Detection of a start bit
When transmitting
When data transmission from the UART2 transfer register is completed
(bit 4 of address 037D
16
= “1”)
When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection
Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
Framing error (see the specifications of clock-asynchronous serial I/O)
Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the T
X
D
2
pin by use of the parity error
signal output function (bit 7 of address 037D
16
= “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the R
X
D
2
pin when a transmission interrupt occurs
The error sum flag (see the specifications of clock-asynchronous serial I/O)
Transfer clock
Transmission / reception control
Other settings
(3) Clock-asynchronous serial I/O mode (used for the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table
1.19.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface).
Interrupt request
generation timing
Note 1: ‘n’ denotes the value 00
16
to FF
16
that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
Table 1.19.8.
Specifications of clock-asynchronous serial I/O mode (used for the SIM interface)