Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Functions
25
The data bank register is made up of the bank selection bits (bits 5 through 3) and the offset bit (bit 2). The
bank selection bits are used to set a bank number for accessing data lying between 40000
16
and
BFFFF
16
. Assigning 1 to the offset bit provides the means to set offsets covering 40000
16
.
Figure 1.8.5 shows the memory location and chip select areas in expansion mode 2.
The area relevant to CS0 ranges from 40000
16
through FFFFF
16
. As for the area from 40000
16
through
BFFFF
16
, the bank number set by use of the bank selection bits are output from the output terminals CS3
- CS1 only in accessing data. In fetching a program, bank 7 (111
2
area from C0000
16
through FFFFF
16
, bank 7 (111
2
) is output from CS3 - CS1 without regard to accessing
data or to fetching a program.
In accessing an area irrelevant to CS0, a chip select signal CS3 (4000
16
- 7FFF
16
), CS2 (8000
16
-
27FFF
16
), and CS1 (28000
16
- 3FFFF
16
) is output depending on the address as in the past.
Figure 1.8.6 shows an example of connecting the MCU with a 4-M byte ROM and to a 128-K byte SRAM.
Connect the chip select of 4-M byte ROM with CS0. Connect M16C’s CS3, CS2, and CS1 with address
inputs AD21, AD20, and AD19 respectively. Connect M16C’s output A19 with address input AD18. Fig-
ure 1.8.7 shows the relationship between addresses of the 4-M byte ROM and those of M16C.
A
e
(
M
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x
e
3
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x
r
n
0
a
a
6
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2
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2
17
8
M
3
0
6
2
2
M
C
D0 to D7
A
0
t
o
A
1
6
A17
A19
RD
CS0
W
R
CS1
CS2
CS3
4
-
M
b
y
t
e
R
O
M
D
Q
0
t
o
D
Q
7
AD0 to AD16
D
1
7
AD18
A
A
A
A
D
D
D
1
2
2
9
0
1
O
C
E
S
1
2
8
-
K
b
y
t
e
S
R
A
M
D
Q
0
t
o
D
Q
7
A
D
0
t
o
A
D
1
6
S
S
2
1
W
O
E
Note: If only one chip select terminal (S1 or S2) is present,
decoding by use of an external circuit is required.
In this mode, memory is
banked every 512 K bytes,
so that data access in differ-
ent banks requires switching
over banks. However, data
on bank boundaries when
offset bit = 0 can be ac-
cessed successively by set-
ting the offset bit to 1, be-
cause in which case the
memory address is offset by
40000
16
.
For example, two
bytes of data located at ad-
dresses 0FFFFF
16
and
100000
16
of 4-Mbyte ROM
can be accessed succes-
sively without having to
change the bank bit by set-
ting the offset bit to 1 and
then accessing addresses
07FFFF
16
and 800000
16
.
On the other hand, the
SRAM’s chip select assumes
that CS0=1 (not selected)
and CS2=0 (selected), so
CS2 with S1. If the SRAM
doesn’t have a bipolar chip
CS0 and CS2 externally.
Figure 1.8.6. An example of connecting the MCU with external
memories in expansion mode 2