Serial I/O
120
Mitsubishi microcomputers
M16C / 62N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.17.9. Serial I/O-related registers (6)
UART2 special mode register 2 (I C bus exclusive use register)
Symbol
Address
When reset
U2SMR2
037616
0016
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(I2C bus exclusive use)
STAC
SWC2
SDHI
I C mode select bit 2
SCL wait output bit
0 : Disabled
1 : Enabled
SDA output stop bit
UART2 initialization bit
Clock-synchronous bit
Refer to Table 1.17.11
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS
0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: UART2 clock
1: 0 output
2
SHTC
Start/stop condition
control bit
Set this bit to “1” in I2C mode
(refer to Table 1.17.12)
2
UART2 special mode register 3 (I C bus exclusive use register)
Symbol
Address
When reset
U2SMR3
037516
0016
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(I C bus exclusive use register)
DL2
SDA digital delay setup
bit
(Note 1, Note 2, Note 3)
DL0
DL1
0 0 0 : Must not be set when using I2C mode
0 0 1 : 1 to 2 cycle(s) of 1/f(XIN)
0 1 0 : 2 to 3 cycles of 1/f(XIN)
0 1 1 : 3 to 4 cycles of 1/f(XIN)
1 0 0 : 4 to 5 cycles of 1/f(XIN)
1 0 1 : 5 to 6 cycles of 1/f(XIN)
1 1 0 : 6 to 7 cycles of 1/f(XIN)
1 1 1 : 7 to 8 cycles of 1/f(XIN)
2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1)
2
b7 b6 b5
Digital delay
is selected
Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit
7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode
register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”,
this register cannot be written to; when read, the value is indeterminate.
Note 2: These bits are initialized to “000” when SDDS = “0”. After a reset, these bits are set to “000”. However,
because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0”
is indeterminate.
Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the
amount of delay increases by about 200 ns, so be sure to take this into account when using the device.