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參數(shù)資料
| 型號： | M30612M8A-402FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機 |
| 文件頁數(shù)： | 32/197頁 |
| 文件大?。?/td> | 2673K |
| 代理商： | M30612M8A-402FP |
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
32
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006
16
). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the X
IN
-X
OUT
drive capacity select bit (bit 5 at address 0007
16
).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 0006
16
), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 0006
16
). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the X
CIN
-X
COUT
drive capacity select bit (bit 3 at address 0006
16
).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 0004
16
) in the memory expan-
sion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 0006
16
) changes to “1” when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f
1
, f
8
, f
32
, f
1SIO2
, f
8SIO2
,f
32SIO2
,f
AD
)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 0006
16
) to “1” and then executing a WAIT instruction.
(5) f
C32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) f
C
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
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