參數資料
型號: M30302M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數: 64/178頁
文件大?。?/td> 2734K
代理商: M30302M4-XXXFP
Electrical characteristics (Vcc = 5V)
155
Mitsubishi microcomputers
M16C / 30 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to
85oC (Note 2), CM15 = “1” unless otherwise specified)
VCC = 5V
Table 1.23.22. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Symbol
Standard
Measuring condition
Max.
Min.
Parameter
Unit
td(BCLK-AD)
Address output delay time
25
ns
th(BCLK-AD)
Address output hold time (BCLK standard)
4
ns
td(BCLK-CS)
Chip select output delay time
25
ns
th(BCLK-CS)
Chip select output hold time (BCLK standard)
4
ns
th(RD-AD)
Address output hold time (RD standard)
(Note1)
td(BCLK-RD)
RD signal output delay time
25
ns
th(BCLK-RD)
RD signal output hold time
0
ns
th(WR-AD)
Address output hold time (WR standard)
(Note1)
td(BCLK-WR)
WR signal output delay time
25
ns
td(BCLK-DB)
Data output delay time (BCLK standard)
40
ns
th(BCLK-DB)
Data output hold time (BCLK standard)
4
ns
td(DB-WR)
Data output delay time (WR standard)
(Note1)
ns
ALE signal output delay time (BCLK standard)
25
ns
th(BCLK-ALE)
ALE signal output hold time (BCLK standard)
– 4
ns
th(ALE-AD)
ALE signal output hold time (Adderss standard)
30
ns
th(BCLK-WR)
WR signal output hold time
0
ns
th(RD-CS)
Chip select output hold time (RD standard)
(Note1)
th(WR-CS)
Chip select output hold time (WR standard)
(Note1)
ns
td(AD-RD)
Post-address RD signal output delay time
ns
0
td(AD-WR)
Post-address WR signal output delay time
ns
0
tdZ(RD-AD)
Address output floating start time
ns
8
th(WR-DB)
Data output hold time (WR standard)
ns
(Note1)
Note 1: Calculated according to the BCLK frequency as follows:
th(RD – AD) =
f(BCLK) X 2
10
9
[ns]
th(WR – AD) =
f(BCLK) X 2
10
9
[ns]
th(RD – CS) =
f(BCLK) X 2
10
9
[ns]
th(WR – CS) =
f(BCLK) X 2
10
9
[ns]
td(DB – WR) =
f(BCLK) X 2
10
9
– 40
[ns]
X 3
td(AD – ALE) =
f(BCLK) X 2
10
9
– 25
[ns]
th(WR – DB) =
f(BCLK) X 2
10
9
[ns]
td(AD-ALE)
ALE signal output delay time (Address standard)
ns
(Note1)
Note 2: Specify a product of -40°C to 85°C to use it.
Figure 1.23.1
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