參數(shù)資料
型號(hào): M30240M5-XXXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 47/231頁
文件大?。?/td> 3508K
代理商: M30240M5-XXXXFP
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121
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications REV. G
Specifications in this manual are tentative and subject to change
Precautions
1.3.1.13 Timer A (Pulse-width Modulation mode)
1. The Timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance
with any of the following procedures:
Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode.
Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to “0” after
the above listed changes have been made.
2. Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the Timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the Timer Ai interrupt request bit does not become “1”.
1.3.1.14 Timer B (Timer mode)
Reading the Timer Bi register while a count is in progress allows reading, with arbitrary timing, the val-
ue of the counter. Reading the Timer Bi register with the reload timing gets “FFFF16”. Reading the Tim-
er Bi register after setting a value in the Timer Bi register with a count halted but before the counter
starts counting gets a proper value.
1.3.1.15 UART2
When using UART2 in clock asynchronous serial I/O mode (UART), use the internal clock only, oth-
erwise, one of the following may occur:
The interrupt may not be issued at the end of the data transmission when the hardware transfers the
data from the transmit buffer to the transmit register.
Data may be corrupted when the hardware transfers data fro the transmit buffer register to the trans-
mit register. This only applies to UART2 asynchronous serial I/O mode and does not apply to UART0
or UART1.
1.3.1.16 USB
When the USB Reset Interrupt Status flag is set to “1”, the contents in the USB internal register (ad-
dresses 030016-033516) will return to their reset values. However, the following registers are not af-
fected by a USB Reset:
USB Control register (USBC)
Frequency Synthesizer Control register (FSC)
USB Endpoint x FIFO (addresses 033816 -033C16)
All LPF pin passive components must be located as close as possible to the LPF pin.
An insulation connector (Ferrite beads) must be connected between the AVss and digital Vss pins,
and between AVcc and digital Vcc pins.
When using DC-DC converter to supply 3.3V to the drive, connect a capacitor between the EXTCAP
pin and the Vss pin. The connection should consist of a 2.2
F capacitor (tantalum capacitor) and a
0.1
F capacitor (ceramic capacitor) connected in parallel. Use a ceramic capacitor equivalent to the
X7R type as a 0.1
F capacitor.
Connect a 27-33
resistor between the USB D+ and USB D- pins to meet USB specification imped-
ance requirements.
Connect a ceramic capacitor (33pF recommended) after the resistor between USB D+ and USB D-
or between USB D+/D- pins and the Vss pin to control the slew rate and rise/fall timing. This cap
should be placed after the 27-33
resistor. See section 1.5 for more details.
Connect a 1.5k
resistor between the EXTCAP pin and the USB D+ pin during normal operation.
Connect a 1.5k
resistor between the P8
3/ATTACH pin and the USB D+ pin and leave the EXTCAP
open when using Attach/Detach function.
Read or write to the USB internal registers (address 030016-033C16) by 8-bit mode only. Accessing
by 16-bit mode will cause incorrect read/write values.
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