參數(shù)資料
型號(hào): M30220FA
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 25/212頁(yè)
文件大?。?/td> 2891K
代理商: M30220FA
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Unde
deeopmen
Preliminary Specifications REV.E
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Stop Mode, Wait Mode
Table 1.9.3. Port status during wait mode
Pin
Status
Port
CK
OUT
Retains status before wait mode
Does not stop
Retains status before stop mode
Does not stop when the WAIT peripheral
function clock stop bit is “0”.
When the WAIT peripheral function clock
stop bit is “1”, the status immediately prior
to entering wait mode is main-tained.
When f
C1
selected
When f
1
, clock devided counter output selected
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. Table 1.9.3 shows the status of the ports in
wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Pin
Status
Port
CK
OUT
Retains status before stop mode
“H”
Retains status before stop mode
When f
C1
selected
When f
1
, clock devided counter output selected
Table 1.9.2. Port status during stop mode
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 0007
16
) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that V
CC
re-
mains above 2V.
Because the oscillation , BCLK, f
1
to f
32
, f
C
, f
C132
, f
C1
, f
C32
and f
AD
stops in stop mode, peripheral functions
such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate
provided that the event counter mode is set to an external pulse, and UART0 to UART2 functions provided
an external clock is selected. Table 1.9.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 0006
16
) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
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