26
Power Control
M
i
t
s
u
M
S
b
i
s
3
M
h
0
I
C
i
m
2
R
i
1
O
c
r
8
C
o
c
o
G
M
m
p
r
P
u
t
u
T
e
r
p
R
s
o
U
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
O
E
Figure 19. State transition diagram of Power control mode
Transition of stop mode, wait mode
Transition of normal mode
Reset
Medium-speed mode
(divided-by-8 mode)
Interrupt
Interrupt
CM10 = “1”
All oscillators stopped
Stop mode
CPU operation stopped
Wait mode
Medium-speed mode
(divided-by-8 mode)
BCLK : f(X
IN
)/8
CM07 = “0” CM06 = “1”
Low-speed mode
High-speed mode
Main clock is oscillating
Sub clock is stopped
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
Main clock is oscillating
Sub clock is oscillating
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Normal mode
(Refer to the following for the transition of normal mode.)
Stop mode
Stop mode
All oscillators stopped
All oscillators stopped
Wait mode
Wait mode
CPU operation stopped
CPU operation stopped
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
CM10 = “1”
Interrupt
CM10 = “1”
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(X
IN
)/8
CM07 = “0”
CM06 = “1”
Medium-speed mode
(divided-by-8 mode)
High-speed mode
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(X
CIN
)
CM07 = “1”
BCLK : f(X
CIN
)
CM07 = “1”
Main clock is oscillating
Sub clock is oscillating
CM07 = “0”
(Note 1, 3)
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM07 = “1”
(Note 2)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
CM07 = “1” (Note 2)
CM05 = “1”
CM05 = “0”
CM05 = “1”
CM04 = “0”
CM04 = “1”
CM06 = “0”
(Notes 1,3)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.