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Timer X
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
240
In pulse width modulation mode, choose functions from those listed in Table 2.4.9. Operations of the
circled items are described below. Figure 2.4.20 shows the operation timing, and Figure 2.4.21 shows the
set-up procedure.
2.4.10 Operation of Timer X (pulse width modulation mode, 16-bit PWM mode selected)
Figure 2.4.20. Operation timing of pulse width modulation mode, 16-bit PWM mode selected
Table 2.4.9. Choosed functions
Operation
Note
Item
Count source
PWM mode
Count start condition
Set-up
O
Internal count source (f1 / f8 / f32 / fc32)
16-bit PWM
8-bit PWM
Timer overflow (TB1/TA0/TXi overflow)
(1) Selected timer overflow is generated with the count start flag set to “1”, the counter performs a
down count on the count source. Also, the TXiINOUT pin outputs an “H” level.
(2) The TXiINOUT pin output level changes from “H” to “L” when a set time period elapses. At this
time, the timer Xi interrupt request bit goes to “1”.
(3) The counter reloads the content of the reload register every time PWM pulses are output for
one cycle, and continues counting.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TXiINOUT outputs an “L” level.
PWM pulse cycle is (216 -1)/fi, whereas “H” level duration is n/fi. However, when “000016” is set
for the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt
request is generated for every PWM output cycle. Also, when “FFFF16” is set for the timer A0
register, the PWM output is “H” level for the entire period, and an interrupt request is generated
for every PWM output cycle.
(fi: Count source frequency f1, f8, f32, fC32 n: Timer value)
1 / fi X (2
–1)
16
Count source
Timer Interrupt
request bit
becoming trigger
PWM pulse output
from TXiINOUT pin
Conditions: Reload register = 000316, when timer overflow is selected in trigger
“H”
“L”
Timer Xi interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
1 / fi X n
Count start flag
“1”
“0”
Set to “1” by software
(1) Start count
(2) Output level “H” to “L”
Note: n = 000016 to FFFE16
(4) Stop count
(3) One period is complete
Cleared to “0” by software
Cleared to “0” when interrupt request is accepted, or cleared by software