參數(shù)資料
型號: M30201M4
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 23/159頁
文件大小: 2319K
代理商: M30201M4
Clock Generating Circuit
Unde
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
23
Pin
States
Port
CLK
OUT
Retains status before wait mode
Does not stop
When f
C
selected
When f
8
, clock devided
counter output selected
Does not stop when the WAIT
peripheral function clock stop bit is “0”.
When the WAIT peripheralfunction
clock stop bit is “1”,the status immedi-
ately prior to entering wait mode is
maintained.
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. Table 1.5 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 1.5. Port status during wait mode
Table 1.4. Port status during stop mode
Pin
States
Port
CLK
OUT
Retains status before stop mode
“H”
When f
C
selected
When f
8
, clock devided
counter output selected
Retains status before stop mode
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 0007
16
) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that V
CC
remains
above 2V.
Because the oscillation of BCLK, f
1
to f
32
, fc, fc
32
, and f
AD
stops in stop mode, peripheral functions such as
the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate
provided that the event counter mode is set to an external pulse, and UART0 functions provided an external
clock is selected. Table 1.4 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 0006
16
) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
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