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Interrupts
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
30
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
Reset
Reset occurs if an “L” is input to the RESET pin.
DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
Watchdog timer interrupt
Generated by the watchdog timer.
Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag
(D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is
the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O
interrupts are maskable interrupts.
Key-input interrupt
A key-input interrupt occurs if an “L” is input to the KI pin.
A-D conversion interrupt
This is an interrupt that the A-D converter generates.
UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
Timer A0 interrupt
This is an interrupts that timer A0 generates.
Timer B0 and timer B2 interrupt
These are interrupts that timer B generates.
Timer X0 to timer X2 interrupt
INT0 and INT1 interrupt
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.