參數(shù)資料
型號(hào)： M2V64S40TP
廠商： Mitsubishi Electric Corporation
英文描述： 64M bit Synchronous DRAM
中文描述： 6400位同步DRAM
文件頁(yè)數(shù)： 23/52頁(yè)
文件大?。?/td> 674K
代理商： M2V64S40TP
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
23
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access
is allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=4)
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random
column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on
DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
Write
Yk
0
10
Dai0
Daj0
Daj1
Dbk0
Write
Yj
0
00
Dbk1 Dbk2
Write
Yl
0
00
Dal0
Dal1
Dal2
Dal3
A11
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
Qaj0
READ
Yj
0
00
Qaj1
Dai0
Dbk0 Dbk1
Write
Yk
0
10
READ
Yl
0
00
Qal0
A11
DQM(x4,x8)
DQMU/L(x16)
相關(guān)PDF資料
PDF描述
M2V64S40BTP 64M bit Synchronous DRAM
M2V64S40BTP-10 64M bit Synchronous DRAM
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