參數(shù)資料
型號(hào): M2V64S40BTP-7
廠商: Mitsubishi Electric Corporation
英文描述: 64M bit Synchronous DRAM
中文描述: 6400位同步DRAM
文件頁數(shù): 29/52頁
文件大小: 674K
代理商: M2V64S40BTP-7
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
29
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70'C, unless otherwise noted)
CAPACITANCE
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ VddQ+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25 'C
1000
mW
Topr
Operating Temperature
0 ~ 70
'C
Tstg
Storage Temperature
-65 ~ 150
'C
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VddQ
Supply Voltage for Output
3.0
3.3
3.6
V
VssQ
Supply Voltage for Output
0
0
0
V
VIH
High-Level Input Voltage all inputs
2.0
Vdd+0.3
V
VIL
Low-Level Input Voltage all inputs
-0.3
0.8
V
Note:*
VIH (max) = Vdd+2.0V AC for pulse width<=3ns acceptable.
VIL(min) = -2V AC for pulse width<=3ns acceptable.
Symbol
Parameter
Test Condition
max.
Unit
CI(A)
Input Capacitance, address pin
VI=Vss
5
pF
CI(C)
Input Capacitance, control pin
f=1MHz
5
pF
CI(K)
Input Capacitance, CLK pin
Vi=25mVrms
4
pF
CI/O
Input Capacitance, I/O pin
6.5
pF
min.
2.5
2.5
2.5
4
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