參數(shù)資料
型號: M2V64S30TP
廠商: Mitsubishi Electric Corporation
英文描述: 64M bit Synchronous DRAM
中文描述: 6400位同步DRAM
文件頁數(shù): 31/52頁
文件大?。?/td> 674K
代理商: M2V64S30TP
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
31
CLK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing through
1.4V.
AC TIMING REQUIREMENTS
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level:
1.4V
Symbol
Parameter
Limits
Unit
note
-8A
-7, -7L
Min.
Max.
Min.
Max.
Min.
Max.
tCLK
CLK cycle time
CL=2
12
10
ns
CL=3
8
10
ns
tCH
CLK High pulse width
3
3
ns
tCL
CLK Low pulse width
3
3
ns
tT
Transition time of CLK
1
10
1
10
ns
tIS
Input Setup time (all inputs)
2
2
ns
tIH
Input Hold time (all inputs)
1
1
ns
tRC
Row Cycle time
70
70
ns
tRCD
Row to Column Delay
20
20
ns
tRAS
Row Active time
48
100000
50
ns
tRP
Row Precharge time
20
20
ns
tWR
Write Recovery time
10
10
ns
tRRD
Act to Act Delay time
16
20
ns
tCCD
Col to Col Delay time
8
10
ns
tRSC
Mode Register Set
Cycle time
16
20
ns
tSRX
Self Refresh Exit time
8
10
ns
tREF
Refresh Interval time
64
64
ms
1
1
1
1
Note:1
The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be
added to the parameter.
100000
-8, -8L
13
10
3
3
1
10
2
1
70
20
50
20
10
20
10
20
10
64
100000
-10, -10L
Min.
Max.
10
64
15
10
4
4
1
3
1
90
30
60
30
10
20
10
20
10
100000
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