參數(shù)資料
型號: M2V64S30DTP-7L
廠商: Mitsubishi Electric Corporation
英文描述: 64M Synchronous DRAM
中文描述: 6400同步DRAM
文件頁數(shù): 19/52頁
文件大小: 674K
代理商: M2V64S30DTP-7L
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
19
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0 at MRS. A burst write starts in
the same cycle as a write command set. (The latency of data input is 0.) The
burst length can be set to 1,2,4,8, and full-page, like burst read operations.
tRCD
CLK
Command
Address
DQ
D0
BL=1
DQ
D0
D1
BL=2
DQ
D0
D1
D2
D3
BL=4
DQ
D0
D1
D2
D3
BL=8
D4
D5
D6
D7
ACT
WRITE
DQ
D0
D1
D2
D3
D4
D5
D6
D7
D8
Dm
D0
D1
M2V64S20B : m=1023
M2V64S30B : m=511
M2V64S40B : m=255
Full Page counter rolls over
and continues to count.
D9
D10
BL=FP
A single write operation is enabled by setting A9=1 at MRS. In a single write
operation, data is written only to the column address specified by the write
command set cycle without regard to the burst length setting. (The latency of data
input is 0.)
[ SINGLE WRITE ]
CLK
Command
Address
X
ACT
WRITE
Y
tRCD
DQ
D0
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M2V64S30TP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM
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