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參數(shù)資料
| 型號： | M2V12D30TP-10L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 128 x 64 pixel format, LED Backlight available |
| 中文描述： | 512M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 21/38頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M2V12D30TP-10L |
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MITSUBISHI
ELECTRIC
-21-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
Notes (continued)
17. A maximum of eight AUTO REFRESH commands can be asserted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK when the clocks are unstable during the power down mode.
19. For command/address and CK & /CK slew rate > 1.0V/ns.
20. IDD7 : Operating current is measured under the conditions
(1).Four Bank are being interleaved with tRC(min),burst mode,address and control inputs on NOP edge
are not changing.Iout = 0mA
(2).Timing Patterns
-DDR200(-10) (100MHz,CL=2) : tCK=10ns, CL=2, BL=4,tRRD=2*tCK, tRCD=3*tCK,
Read with autoprecharge
Setup:A0 N A1 R0 A2 R1 A3 R2
Read :A0 R3 A1 R0 A2 R1 A3 R2 -repeat the same timing with random address changing
50% of data changing at every transfer
-DDR266B(-75) (133MHz,CL=2.5) : tCK=7.5ns, CL=2.5, BL=4,tRRD=2*tCK, tRCD=3*tCK,
Read with autoprecharge
Setup:A0 N A1 R0 A2 R1 A3 R2 N R3
Read :A0 N A1 R0 A2 R1 A3 R2 N R3 -repeat the same timing with random address changing
50% of data changing at every transfer
-DDR266A(-75A) (133MHz,CL=2) : tCK=7.5ns, CL=2, BL=4,tRRD=2*tCK, tRCD=3*tCK,
Read with autoprecharge
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 -repeat the same timing with random address changing
50% of data changing at every transfer
*Legend: A=Activate,R=Read, P=Precharge, N=NOP
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