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參數(shù)資料
| 型號： | M2V12D20TP-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 128 x 64 pixel format, LED Backlight available |
| 中文描述： | 512M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M2V12D20TP-75 |
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MITSUBISHI
ELECTRIC
-26-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
After tRCD time from the bank activation, a WRITE command can be issued. 1st input data is sampled
at the WRITE command with data strobe input, followed by (BL-1) data being written into RAM.
The Burst Length is BL. The start address is specified by A12-A11,A9-A0(x4)/A11,A9-A0(x8), and the
address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any
active bank, so the row precharge time (tRP) can be hidden during the continuous input data by
interleaving the multiple banks. The write recovery time (tWR) is required from the last written data to
the next PRE command. When A10 is high in a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge operation is completed. The next ACT command can be issued after tDAL
from the last input data cycle.
WRITE
Multi Bank Interleaving WRITE (BL=8)
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
00
WRITE
00
WRITE
0
0
10
ACT
Xb
10
0
10
tRCD
D
tRCD
D
PRE
Xa
0
00
PRE
DQS
/CLK
CLK
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
Db1
Db2
Db3
Db4
Db5
Db6
Db7
Xa
Ya
Yb
Xb
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2S12D30TP-75 | 128 x 64 pixel format, LED Backlight available |
| M2V12D30TP-75 | 128 x 64 pixel format, LED Backlight available |
| M2V28D20ATP-75 | 128M Double Data Rate Synchronous DRAM |
| M2V28D30ATP-10 | 353620600 |
| M2V28D30ATP-75 | 128M Double Data Rate Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V28D20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D20ATP-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D30ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D30ATP-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D40ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
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