參數(shù)資料
型號(hào)： M2S56D20ATP-75
廠商： Mitsubishi Electric Corporation
英文描述： 256M Double Data Rate Synchronous DRAM
中文描述： 256M雙數(shù)據(jù)速率同步DRAM
文件頁數(shù)： 5/40頁
文件大小： 768K
代理商： M2S56D20ATP-75
5
MITSUBISHI ELECTRIC
Mar. '02
MITSUBISHI LSIs
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
CLK, /CLK
Input
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh.After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
Input
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
Input / Output
DQS
VDD, VSS
Power Supply Power Supply for the memory array and peripheral circuitry.
VDDQ, VSSQ
Power Supply VDDQ and VSSQ are supplied to the Output Buffers only.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output pin during Read operation, input pin during Write
operation. Edge-aligned with read data, placed at the centered of write data
to capture the write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15.
SYMBOL
TYPE
DESCRIPTION
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with the input data
during a WRITE operations. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
Input / Output
VREF
Input
SSTL_2 reference voltage.
相關(guān)PDF資料
PDF描述
M2S56D20ATP-75A 256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75AL 256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75L 256M Double Data Rate Synchronous DRAM
M2S56D20ATP75A 256M Double Data Rate Synchronous DRAM
M2S56D30AKT 256M Double Data Rate Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2S56D20ATP75A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75AL 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D20ATP-75L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2S56D20TP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
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