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參數(shù)資料
| 型號(hào)： | M2S12D30TP-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 128 x 64 pixel format, LED Backlight available |
| 中文描述： | 512M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 32/38頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M2S12D30TP-10 |
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MITSUBISHI
ELECTRIC
-32-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
Burst write operation can be interrupted by Write to any bank. Random column access is allowed.
WRITE to WRITE interval is 1 CLK minimum.
[Write interrupted by Write]
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column
access is allowed. Internal WRITE to READ command interval(tWTR) is 1 CLK minimum. The
input data masked by DM in the interrupted READ cycle is "don't care". tWTR is referenced from
the first positive edge after the last data input.
Write Interrupted by Read (BL=8, CL=2.5)
Command
A0-9,11
A10
BA0,1
DQ
WRITE
Yi
0
00
READ
Yj
0
00
Dai0
Dai1
Qaj0
Qaj1 Qaj2
Qaj3
QS
Qaj4
Qaj5
Qaj6
Qaj7
DM
tWTR
/CLK
CLK
Write Interrupted by Write (BL=8)
Command
A0-9,11-12
A10
BA0,1
WRITE
Yi
0
00
WRITE
Yk
0
10
WRITE
Yj
0
00
WRITE
Yl
0
00
DQ
Dai1
Daj1
Daj3
Dak1
Dak3
Dak5
Dal1
DQS
Dal2 Dal3
Dal5 Dal6
Dal7
Dal4
Dal0
Dak4
Dak2
Dak0
Dai0
Daj0
Daj2
/CLK
CLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2V12D30TP-10 | 128 x 64 pixel format, LED Backlight available |
| M2S12D20TP-10L | 128 x 64 pixel format, LED Backlight available |
| M2V12D20TP-10L | 128 x 64 pixel format, LED Backlight available |
| M2S12D30TP-10L | 128 x 64 pixel format, LED Backlight available |
| M2V12D30TP-10L | 128 x 64 pixel format, LED Backlight available |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2S12D30TP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:512M Double Data Rate Synchronous DRAM |
| M2S12D30TP-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:512M Double Data Rate Synchronous DRAM |
| M2S12D30TP-75L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:512M Double Data Rate Synchronous DRAM |
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