參數(shù)資料
型號(hào): M2S12D20TP-75
廠商: Mitsubishi Electric Corporation
英文描述: 128 x 64 pixel format, LED Backlight available
中文描述: 512M雙數(shù)據(jù)速率同步DRAM
文件頁(yè)數(shù): 19/38頁(yè)
文件大?。?/td> 754K
代理商: M2S12D20TP-75
MITSUBISHI
ELECTRIC
-19-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
AC TIMING REQUIREMENTS(Continued)
(Ta=0 ~ 70
o
C, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)
Output Load Condition
DQ
Output Timing
Measurement
Reference Point
V
REF
V
REF
DQS
VREF
Zo=50
30pF
50
VOUT
VTT=VREF
Min.
45
Max
120,000
Min.
50
Max
120,000
tRAS
Row Active time
ns
tRC
Row Cycle time(operation)
65
70
ns
tRFC
Auto Ref. to Active/Auto Ref. command period
75
80
ns
tRCD
Row to Column Delay
20
20
ns
tRP
Row Precharge time
20
20
ns
tRRD
Act to Act Delay time
15
15
ns
tWR
Write Recovery time
15
15
ns
tDAL
Auto Precharge write recovery + precharge time
35
35
ns
tWTR
Internal Write to Read Command Delay
1
1
tCK
tXSNR Exit Self Ref. to non-Read command
75
80
ns
tXSRD
Exit Self Ref. to -Read command
200
200
tCK
tXPNR Exit Power down to command
1
1
tCK
tXPRD
Exit Power down to -Read command
1
1
tCK
18
tREFI
Average Periodic Refresh interval
7.8
7.8
μ
s
17
-10
Unit
Notes
Symbol
AC Characteristics Parameter
-75
CAPACITANCE
(Ta=0 ~ 70
o
C, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)
Min. Max.
2.0
2.0
2.0
4.0
CI(A)
CI(C)
CI(K)
CI/O
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CLK pin
I/O Capacitance, I/O, DQS, DM pin
VI=1.25v
f=100MHz
VI=25mVrms
3.0
3.0
3.0
5.0
pF
pF
pF
pF
11
11
11
11
0.25
0.50
0.50
Notes
Limits
Symbol
Parameter
Test Condition
Unit
Delta
Cap.(Max.)
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