參數(shù)資料
型號(hào)： M29W040-200NZ6TR
廠商： 意法半導(dǎo)體
英文描述： 4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
中文描述： 4兆位512KB的× 8，統(tǒng)一座低電壓?jiǎn)坞娫撮W存
文件頁(yè)數(shù)： 14/31頁(yè)
文件大小： 205K
代理商： M29W040-200NZ6TR
Symbol
Alt
Parameter
M29W040
Unit
-150
-200
V
CC
= 2.7V to 3.6V
V
CC
= 2.7V to 3.6V
Min
Max
Min
Max
t
AVAV
t
WC
Address Validto Next Address Valid
150
200
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
65
80
ns
t
DVWH
t
DS
Input Valid to Write Enable High
65
80
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip EnableHigh
0
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
35
35
ns
t
AVWL
t
AS
Address Validto WriteEnable Low
0
0
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
65
65
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μ
s
t
WHQV1(1)
Write Enable High to Output Valid (Program)
12
12
μ
s
t
WHQV2(1)
Write Enable High to Output Valid
(Block Erase)
1.5
30
1.5
30
sec
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
Note:
1. Time is measured to Data Polling or ToggleBit, t
WHQV
= t
WHQ7V
+ t
Q7VQV
.
Table13B. Write AC Characteristics,Write Enable Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C or –40 to 85
°
C)
Block Erase (BE) instruction
. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on thirdcycleafterthetwocodedcycles.The Block
Erase Confirm command 30h is written on sixth
cycle after another two coded cycles. During the
input of the second command an address within
theblockto be erasedis givenandlatchedinto the
memory. Additional Block Erase confirm com-
mands and block addresses can be written sub-
sequentlyto erase other blocks in parallel,without
further coded cycles. The erase will start after the
Erase timeout period (see Erase Timer Bit DQ3
description). Thus, additional Block Erase com-
mands mustbe givenwithinthisdelay.The inputof
a newBlockErasecommandwillrestartthetimeout
period. The status of the internal timer can be
monitoredthroughthe levelofDQ3,ifDQ3is’0’the
Block Erase Command has been given and the
timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.Cis erasingthe block(s).
DuringErasetimeout,anycommanddifferentfrom
30h will abort the instruction and reset the device
to read arraymode. It is notnecessaryto program
the block with 00h as the P/E.C. will do this auto-
matically before erasing to FFh. Read operations
after the sixth rising edge of W or E output the
statusregister bits.
Duringtheexecutionof theerasebytheP/E.C.,the
memoryaccepts onlythe ES(EraseSuspend)and
RST (Reset) instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
whenit hascompleted.TheToggleBitDQ6toggles
during the erase operation. It stops when erase is
completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure becauseerasure has not completedeven
after the maximum number of erase cycles have
been executed.In this case,it will be necessaryto
input a Reset (RST) to the command interface in
order to reset the P/E.C.
14/31
M29W040
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