參數(shù)資料
型號: M29KW032E90N3T
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Uniform Block 3V Supply LightFlash⑩ Memory
中文描述: 32兆位的2Mb x16插槽,統(tǒng)一座3V電源LightFlash⑩記憶
文件頁數(shù): 8/30頁
文件大?。?/td> 234K
代理商: M29KW032E90N3T
M29KW032E
8/30
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 3, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 10, Read Mode AC Waveforms,
and Table 13, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 14 and 15, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
be held within V
CC
± 0.2V. For the Standby current
level see Table 12, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
, for Program or Erase operations un-
til the operation completes.
Automatic Standby.
If CMOS levels (V
CC
± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3, Bus Operations.
Table 3. Bus Operations
Note: 1. X = V
IL
or V
IH
.
2. XX = V
IL
, V
IH
or V
HH
3. Not necessary for Auto Select or Read/Reset commands.
4. When reading the Status Register during Program or Erase operations, V
PP
must be kept at V
HH
.
Operation
E
G
W
V
PP
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15-DQ0
Bus Read
V
IL
V
IL
V
IH
XX
(4)
Cell Address
Data Output
Bus Write
V
IL
V
IH
V
IL
V
HH(3)
Command Address
Data Input
Output Disable
X
V
IH
V
IH
X
X
Hi-Z
Standby
V
IH
X
X
X
X
Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
IH
XX
A0 = V
IL
, A1 = V
IL
,
Others V
IL
or V
IH
0020h
Read Device Code
V
IL
V
IL
V
IH
XX
A0 = V
IH
, A1 = V
IL
,
Others V
IL
or V
IH
88ACh
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