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    參數(shù)資料
    型號(hào): M29F400BT-90N1
    廠商: 意法半導(dǎo)體
    英文描述: 4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory
    中文描述: 4兆位512KB的x8或256Kb的x16插槽,啟動(dòng)座單電源閃存
    文件頁(yè)數(shù): 4/22頁(yè)
    文件大?。?/td> 208K
    代理商: M29F400BT-90N1
    M29F400BT, M29F400BB
    4/22
    SIGNAL DESCRIPTIONS
    See Figure 1, Logic Diagram, and Table 1, Signal
    Names, for a brief overview of the signals connect-
    ed to this device.
    Address Inputs (A0-A17).
    The Address Inputs
    select the cells in the memory array to access dur-
    ing Bus Read operations. During Bus Write opera-
    tions they control the commands sent to the
    Command Interface of the internal state machine.
    Data Inputs/Outputs (DQ0-DQ7).
    The Data In-
    puts/Outputs output the data stored at the selected
    address during a Bus Read operation. During Bus
    Write operations they represent the commands
    sent to the Command Interface of the internal state
    machine.
    Data Inputs/Outputs (DQ8-DQ14).
    The Data In-
    puts/Outputs output the data stored at the selected
    address during a Bus Read operation when BYTE
    is High, V
    IH
    . When BYTE is Low, V
    IL
    , these pins
    are not used and are high impedance. During Bus
    Write operations the Command Register does not
    use these bits. When reading the Status Register
    these bits should be ignored.
    Data Input/Output or Address Input (DQ15A-1).
    When BYTE is High, V
    IH
    , this pin behaves as a
    Data Input/Output pin (as DQ8-DQ14). When
    BYTE is Low, V
    IL
    , this pin behaves as an address
    pin; DQ15A–1 Low will select the LSB of the Word
    on the other addresses, DQ15A–1 High will select
    the MSB. Throughout the text consider references
    to the Data Input/Output to include this pin when
    BYTE is High and references to the Address In-
    puts to include this pin when BYTE is Low except
    when stated explicitly otherwise.
    Chip Enable (E).
    The Chip Enable, E, activates
    the memory, allowing Bus Read and Bus Write op-
    erations to be performed. When Chip Enable is
    High, V
    IH
    , all other pins are ignored.
    Output Enable (G).
    The Output Enable, G, con-
    trols the Bus Read operation of the memory.
    Write Enable (W).
    The Write Enable, W, controls
    the Bus Write operation of the memory’s Com-
    mand Interface.
    Reset/Block Temporary Unprotect (RP).
    The Re-
    set/Block Temporary Unprotect pin can be used to
    apply a Hardware Reset to the memory or to tem-
    porarily unprotect all Blocks that have been pro-
    tected.
    A Hardware Reset is achieved by holding Reset/
    Block Temporary Unprotect Low, V
    IL
    , for at least
    t
    PLPX
    . After Reset/Block Temporary Unprotect
    goes High, V
    IH
    , the memory will be ready for Bus
    Read and Bus Write operations after t
    PHEL
    or
    t
    RHEL
    , whichever occurs last. See the Ready/Busy
    Output section, Table 17 and Figure 11, Reset/
    Temporary Unprotect AC Characteristics for more
    details.
    Holding RP at V
    ID
    will temporarily unprotect the
    protected Blocks in the memory. Program and
    Erase operations on all blocks will be possible.
    The transition from V
    IH
    to V
    ID
    must be slower than
    t
    PHPHH
    .
    Ready/Busy Output (RB).
    The Ready/Busy pin
    is an open-drain output that can be used to identify
    when the memory array can be read. Ready/Busy
    is high-impedance during Read mode, Auto Select
    mode and Erase Suspend mode.
    After a Hardware Reset, Bus Read and Bus Write
    operations cannot begin until Ready/Busy be-
    comes high-impedance. See Table 17 and Figure
    11, Reset/Temporary Unprotect AC Characteris-
    tics.
    During Program or Erase operations Ready/Busy
    is Low, V
    OL
    . Ready/Busy will remain Low during
    Read/Reset commands or Hardware Resets until
    the memory is ready to enter Read mode.
    The use of an open-drain output allows the Ready/
    Busy pins from several memories to be connected
    to a single pull-up resistor. A Low will then indicate
    that one, or more, of the memories is busy.
    Byte/Word Organization Select (BYTE).
    The Byte/
    Word Organization Select pin is used to switch be-
    tween the 8-bit and 16-bit Bus modes of the mem-
    ory. When Byte/Word Organization Select is Low,
    V
    IL
    , the memory is in 8-bit mode, when it is High,
    V
    IH
    , the memory is in 16-bit mode.
    V
    CC
    Supply Voltage.
    The V
    CC
    Supply Voltage
    supplies the power for all operations (Read, Pro-
    gram, Erase etc.).
    The Command Interface is disabled when the V
    CC
    Supply Voltage is less than the Lockout Voltage,
    V
    LKO
    . This prevents Bus Write operations from ac-
    cidentally damaging the data during power up,
    power down and power surges. If the Program/
    Erase Controller is programming or erasing during
    this time then the operation aborts and the memo-
    ry contents being altered will be invalid.
    A 0.1μF capacitor should be connected between
    the V
    CC
    Supply Voltage pin and the V
    SS
    Ground
    pin to decouple the current surges from the power
    supply. The PCB track widths must be sufficient to
    carry the currents required during program and
    erase operations, I
    CC4
    .
    Vss Ground.
    The V
    SS
    Ground is the reference
    for all voltage measurements.
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