參數(shù)資料
型號: M29DW640D90N6
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
中文描述: 64兆位(8兆x8或4Mb的x16插槽,多行,頁,引導(dǎo)塊)3V電源快閃記憶體
文件頁數(shù): 54/56頁
文件大小: 942K
代理商: M29DW640D90N6
M29DW640D
54/56
REVISION HISTORY
Table 32. Document Revision History
Date
Version
Revision Details
10-Dec-2002
1.0
Document written
27-Feb-2003
1.1
Typical after 100k W/E Cycles column removed from
Table 7., Program, Erase Times and
Program, Erase Endurance Cycles
, and Data Retention and Erase Suspend Latency
Time parameters added. Device code corrected. Address on DQ7-DQ0 modified for the
cycle No.2 of the Read Device code in
Table 3., Bus Operations, BYTE = V
IL
.
Lead-free package options E and F added to
Table 22., Ordering Information Scheme
.
01-Apr-2003
1.2
Document Status promoted to Preliminary Data. Page mode added, Appendix C
“Extended Memory Block” added. V
SS
signal description clarified. Parameter I
ID
removed
from DC Characteristics Table. Read CFI Query command address clarified. Program
Suspend Latency time added to
Table 7., Program, Erase Times and Program, Erase
Endurance Cycles
. Dual operations section added.
15-May-2003
1.3
Note added to
Table 22., Ordering Information Scheme
.
Table 20., TSOP48 – 48 lead
Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
and
Figure
19., TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
,
modified.
Data modified at addresses 4Ah and 4Fh in Table
28
,
Primary Algorithm-Specific
Extended Query Table
and at address 2Ch in Table
27
,
Device Geometry Definition
.
18-Jul-2003
2.0
Note 1 removed from: Figures
5
and
6
, Block Address (x8 and x16, respectively), and
from Table
23
,
Block Addresses
. RB bit is High-Z (instead of 1), in Table
8
.
Auto Select Command
description modified. Extended Memory Block size modified in
Appendix
C
.
15-Sep-2003
2.1
Figures
15
and
16
, Toggle and Alternative Toggle Bits Mechanisms added.
Table 16, Toggle and Alternative Toggle Bits AC Characteristics added.
Address 38h modified, addresses 39h to 3Ch added in
Device Geometry Definition
.
Address 44h modified in
Table 28., Primary Algorithm-Specific Extended Query Table
.
07-Oct-2003
2.2
Figures
15
and
16
, Toggle and Alternative Toggle Bits Mechanisms modified; and Notes 1
and 2 added.
Table 18., Toggle and Alternative Toggle Bits AC Characteristics
updated.
Figure 8., Toggle Flowchart
renamed and modified, Note added.
07-Nov-2003
2.3
Bank Address modified in the Auto Select command, Read CFI Query command and
COMMON FLASH INTERFACE (CFI) sections.
Addresses for Read CFI Query command modified in the Read CFI command section.
18-Nov-2003
2.4
Vcc minimum value updated in
Table 12., Operating and AC Measurement Conditions
.
V
PP
and I
PP
test conditions updated in
Table 14., DC Characteristics
.
Customer Lockable Extended Block mechanism modified in
APPENDIX C., EXTENDED
MEMORY BLOCK
.
APPENDIX D., BLOCK PROTECTION
updated: Note 1 added in the In-System
Technique section and Note 2 added below
Figure 23., In-System Equipment Group
Protect Flowchart
.
19-Dec-2003
2.5
Architecture Identifier updated in Table 22, Part Numbering Scheme.
Customer Lockable Extended Block mechanism modified in
APPENDIX C., EXTENDED
MEMORY BLOCK
.
APPENDIX D., BLOCK PROTECTION
updated: Note 1 updated in the In-System
Technique section and Note 2 updated below
Figure 23., In-System Equipment Group
Protect Flowchart
.
12-Aug-2004
3.0
Figure 2., Logic Diagram
and
Figure 3., TSOP Connections
updated.
Table 9., Dual Operations Allowed In Other Banks
and
Table 10., Dual Operations
Allowed In Same Bank
updated in
DUAL OPERATIONS AND MULTIPLE BANK
ARCHITECTURE
section.
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