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參數(shù)資料
| 型號： | M28LV64-300XP6 |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 64K 8K x 8 LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION |
| 中文描述： | 64K的8K的× 8低電壓并聯(lián)EEPROM，帶有軟件數(shù)據保護 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 127K |
| 代理商： | M28LV64-300XP6 |
M28LV64
64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
May 1997
1/18
This is information on a product still in production butnot recommendedfor new designs.
AI01538B
13
A0-A12
W
DQ0-DQ7
VCC
M28LV64
G
E
VSS
8
RB *
Figure 1. Logic Diagram
28
1
PDIP28 (P)
PLCC32 (K)
A0 - A12
Address Input
DQ0 - DQ7
Data Input / Output
W
Write Enable
E
Chip Enable
G
Output Enable
RB
Ready / Busy
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
FASTACCESS TIME: 200ns
SINGLE LOW VOLTAGEOPERATION
LOW POWER CONSUMPTION
FASTWRITE CYCLE:
– 64 BytesPage Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Ready/BusyOpenDrain Output
(only on the M28LV64)
– Data Polling
– Toggle Bit
PAGELOAD TIMER STATUS BIT
HIGH RELIABILITYSINGLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance>100,000Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATAPROTECTION
TheM28LV64 is replaced by the
M28C64-xxW
DESCRIPTION
The M28LV64 is an 8K x 8 low power Parallel
EEPROM fabricated with SGS-THOMSON pro-
prietary single polysilicon CMOS technology. The
device offers fast access time with low power dis-
sipation and requiresa 2.7V to 3.6V powersupply.
TSOP28 (N)
8x13.4mm
28
1
SO28 (MS)
300 mils
Note:
* RB function is only available on the M28LV64.
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