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參數資料
| 型號： | M28F201-70XK3TR |
| 廠商： | 意法半導體 |
| 英文描述： | 2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| 中文描述： | 2 MB的256K × 8，芯片擦除閃存 |
| 文件頁數： | 16/21頁 |
| 文件大小： | 179K |
| 代理商： | M28F201-70XK3TR |
PRESTO F ERASE ALGORITHM
The PRESTO F Erase Algorithm guarantees that
the device will be erased in a reliable way. The
algorithm first programs all bytes to 00h in order to
ensureuniform erasure. The programmingfollows
the PRESTO F Programming Algorithm. Erase is
set-up by writing 20h to the command register,the
erasure is started by repeating this write cycle.
Erase Verify is set-up by writing A0h to the com-
mandregistertogetherwith theaddressof the byte
to beverified.Thesubsequentread cyclereadsthe
datawhichiscomparedto FFh.Erase Verifybegins
at address0000h andcontinuesto thelastaddress
or until the comparison of the data to FFh fails. If
this occurs, theaddressof the lastbyte checkedis
stored and a new Erase operation performed.
EraseVerifythencontinuesfromthe addressof the
stored location.
PRESTO F PROGRAM ALGORITHM
The PRESTO F Programming Algorithm applies a
series of 10
μ
s programming pulses to a byte until
a correct verify occurs. Up to 25 programming
operations are allowed for one byte. Program is
set-upby writing 40hto thecommand register, the
programming is started after the next write cycle
which also latches the address and data to be
programmed. Program Verify is set-up by writing
C0h to the command register, followed by a read
cycle and a compare of the data read to the data
expected.During Program andProgram Verify op-
erations a MARGIN MODE circuit is activated to
guaranteethat thecellisprogrammedwith asafety
margin.
PROGRAM
ALL
BYTES TO 00h
AI00649
n=0, Addr=00000h
Last
Addr
ERASE SET-UP
Wait 10ms
ERASE VERIFY
Latch Addr.
READ DATA OUTPUT
Data
OK
Wait 6
μ
s
++n
1000
Addr++
READ COMMAND
VPP= 12V
VPP<
6.5V
FAIL
VPP< 6.5V, PASS
YES
NO
YES
NO
YES
NO
Figure12. ErasingFlowchart
AI00677
n = 0
Last
Addr
PROGRAM VERIFY
Wait 10
μ
s
PROGRAM SET-UP
Latch Addr, Data
READ DATA OUTPUT
Data
OK
Wait 6
μ
s
++n
= 25
Addr++
READ COMMAND
VPP= 12V
VPP<
6.5V
FAIL
VPP< 6.5V, PASS
YES
NO
YES
NO
YES
NO
Figure 13. ProgrammingFlowchart
16/21
M28F201
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M28F201-70XK6R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70XK6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70XN1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70XN1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
| M28F201-70XN3R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mb 256K x 8, Chip Erase FLASH MEMORY |
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