參數(shù)資料
型號: M28C64X-150MS6
廠商: 意法半導(dǎo)體
英文描述: 64 Kbit 8Kb x8 Parallel EEPROM
中文描述: 64千位8KB的x8并行的EEPROM
文件頁數(shù): 3/15頁
文件大?。?/td> 100K
代理商: M28C64X-150MS6
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
– 40 to 125
°
C
T
STG
Storage TemperatureRange
– 65 to 150
°
C
V
CC
Supply Voltage
– 0.3 to 6.5
V
V
IO
Input/Output Voltage
– 0.3 to V
CC
+0.6
V
V
I
Input Voltage
– 0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
2000
V
Note:
Except for the rating ”O(jiān)perating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the Operating sections of this specification is not implied. Exposure toAbsoluteMaximum Rating conditions for extended
periods may affect device reliability.Refer also tothe STMicroelectronics SURE Program and other relevant quality documents.
Table2. AbsoluteMaximumRatings
Mode
E
G
W
DQ0 - DQ7
Read
V
IL
V
IL
V
IH
Data Out
Write
V
IL
V
IH
V
IL
Data In
Standby / Write Inhibit
V
IH
X
X
Hi-Z
Write Inhibit
X
X
V
IH
Data Out or Hi-Z
Write Inhibit
X
V
IL
X
Data Out or Hi-Z
Output Disable
X
V
IH
X
Hi-Z
Note:
X = V
IH
or V
IL
Table3. OperatingModes
DataIn/Out(DQ0- DQ7).
Dataiswrittento orread
from the M28C64Cthrough the I/O pins.
WriteEnable(W).
TheWriteEnableinputcontrols
the writing of datato the M28C64C.
Ready/Busy (RB).
Ready/Busy is an open drain
output that can be used to detect the end of the
internalwrite cycle.
OPERATION
In orderto preventdata corruptionand inadvertent
write operations during power-up, a Power On
Reset(POR)circuitresetsallinternalprogramming
cicuitry. Access to the memory in write mode is
allowed after a power-upas specifiedin Table6.
Read
The M28C64C is accessed like a static RAM.
When E and G are low with W high, the data
addressed is presented on the I/O pins. The I/O
pinsarehighimpedancewheneitherGorEishigh.
Write
Write operations are initiated when both W and E
arelow andG is high.TheM28C64Csupportsboth
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurslast and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operationis internallytimed until completion.
Page Write
Page write allows up to 32 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A5 - A12 must be the
samefor all bytes.The pagewrite can beinitiated
during any bytewrite operation.
Following the first byte write instruction the host
may send another addressand dataup to a maxi-
mumof 100
μ
s aftertherisingedge of EorWwhich
ever occurs first (t
BLC
). If a transition of E or W is
not detected within 100
μ
s, the internal program-
ming cycle will start.
3/15
M28C64C, M28C64X
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