參數(shù)資料
型號(hào): M27W800-150F6TR
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit 1Mb x 8 or 512Kb x 16 Low Voltage UV EPROM and OTP EPROM
中文描述: 8兆1兆× 8或512KB × 16低壓紫外線存儲(chǔ)器和OTP存儲(chǔ)器
文件頁數(shù): 2/15頁
文件大小: 140K
代理商: M27W800-150F6TR
M27W800
2/15
Figure 2B. LCC Connections
AI03603
A
A14
A15
Q7
Q14
Q
23
Q0
Q8
Q1
Q
Q
N
Q
A4
A3
A2
A1
A0
E
VSS
12
A
A16
BYTEVPP
VSS
Q15A–1
1
A
A13
A
Q6
44
V
A
M27W800
A
A12
Q
34
Q
G
Q
Q
V
Q
A
A
A
N
Figure 2A. DIP Connections
G
Q0
Q8
Q1
Q9
A3
A2
A1
A0
E
VSS
A13
A14
A15
A16
BYTEVPP
VSS
Q15A-1
Q7
Q14
Q6
Q13
A12
Q5
Q12
Q2
Q10
Q3
Q11
VCC
Q4
A9
A10
A8
A17
A7
A6
A5
A4
A18
NC
AI03602
M27W800
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
32
31
30
29
28
27
26
25
24
23
22
20
21
19
18
42
41
39
38
37
36
35
34
33
A11
40
Table 1. Signal Names
A0-A18
Address Inputs
Q0-Q7
Data Outputs
Q8-Q14
Data Outputs
Q15A–1
Data Output / Address Input
E
Chip Enable
G
Output Enable
BYTEV
PP
Byte Mode / Program Supply
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
DEVICE OPERATION
The operating modes of the M27W800 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27W800 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV
PP
pin. When BYTEV
PP
is at V
IH
the Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEV
PP
pin is at V
IL
the Byte-wide or-
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at V
IL
the
lower 8 bits of the 16 bit data are selected and with
A–1 at V
IH
the upper 8 bits of the 16 bit data are
selected.
The M27W800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
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