參數(shù)資料
型號: M27W256-80K6TR
廠商: 意法半導(dǎo)體
英文描述: Dual 1-of-4 Data Selectors/Multiplexers 16-SOIC 0 to 70
中文描述: 256千位的32KB × 8低壓紫外線可擦寫可編程只讀存儲器和OTP存儲器
文件頁數(shù): 8/15頁
文件大小: 101K
代理商: M27W256-80K6TR
M27W256
8/15
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows to pro-
gram the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100
μ
s program pulses to each byte until a cor-
rect verify occurs (see Figure 7). During program-
ming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. Nooverprogram pulse is applied since the
verify in MARGIN MODE at V
CC
much higher than
3.6V provides necessary margin to each pro-
grammed cell.
Program Inhibit
Programming of multiple M27W256s in parallel
with different data is also easily accomplished. Ex-
cept for E, all likeinputs including G of the parallel
M27W256 may be common. ATTL low level pulse
applied to a M27W256’s E input, with V
PP
at12.75
V, will program that M27W256. A highlevel Einput
inhibits the other M27W256s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that theywere correct-
ly programmed. The verify is accomplished with G
at V
IL
, E at V
IH
, V
PP
at 12.75V and V
CC
at 6.25V.
Figure 6. Programming and Verify Modes AC Waveforms
tAVEL
VALID
AI00759
A0-A14
Q0-Q7
VPP
VCC
G
DATA IN
DATA OUT
E
tQVEL
tVPHEL
tVCHEL
tEHQX
tELEH
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 7. Programming Flowchart
AI00707D
n = 0
Last
Addr
VERIFY
P = 100
μ
s Pulse
++n
= 25
++ Addr
VCC= 6.25V, VPP= 12.75V
FAIL
CHECK ALL WORDS
1st: VCC= 5V
2nd: VCC= 2.7V
YES
NO
YES
NO
YES
NO
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