參數(shù)資料
型號(hào): M27W201-80K
廠商: 意法半導(dǎo)體
英文描述: Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
中文描述: 2兆位的256Kb × 8低壓紫外線可擦寫可編程只讀存儲(chǔ)器和OTP存儲(chǔ)器
文件頁(yè)數(shù): 8/16頁(yè)
文件大?。?/td> 170K
代理商: M27W201-80K
M27W201
8/16
Figure 7. Programming Flowchart
AI00715D
n = 0
Last
Addr
VERIFY
P = 100
μ
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL BYTES
1st: VCC = 5V
2nd: VCC = 2.7V
YES
NO
YES
NO
YES
NO
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100μs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at V
CC
much
higher than 3.6V, provides the necessary margin
to each programmed cell.
Program Inhibit
Programming of multiple M27W201s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27W201 may be common. A TTL low level pulse
applied to a M27W201's P input, with E low and
V
PP
at 12.75V, will program that M27W201. A high
level E input inhibits the other M27W201s from be-
ing programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at V
IL
, P at V
IH
, V
PP
at 12.75V and V
CC
at
6.25V.
Figure 6. Programming and Verify Modes AC Waveforms
tAVPL
VALID
AI00720
A0-A17
Q0-Q7
VPP
VCC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM
VERIFY
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