參數(shù)資料
型號: M27V402-120N1TR
廠商: 意法半導體
英文描述: Quadruple 2-Input Positive-NOR Gates 14-PDIP 0 to 70
中文描述: 4兆位的256Kb × 16低壓紫外線存儲器和OTP存儲器
文件頁數(shù): 7/15頁
文件大?。?/td> 101K
代理商: M27V402-120N1TR
7/15
M27V402
Table 9. Programming Mode DC Characteristics
(1)
(T
A
= 25
°
C; V
CC
= 6.25V
±
0.25V; V
PP
= 12.75V
±
0.25V)
Symbol
Parameter
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 10. Programming Mode AC Characteristics
(1)
(T
A
= 25
°
C; V
CC
= 6.25V
±
0.25V; V
PP
= 12.75V
±
0.25V)
Symbol
Alt
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0
V
IN
V
CC
±
10
μ
A
I
CC
Supply Current
50
mA
I
PP
Program Current
E = V
IL
50
mA
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= –400
μ
A
2.4
V
V
ID
A9 Voltage
11.5
12.5
V
Parameter
Test Condition
Min
Max
Unit
t
AVEL
t
AS
Address Valid to Chip Enable Low
2
μ
s
t
QVEL
t
DS
Input Valid to Chip Enable Low
2
μ
s
t
VPHEL
t
VPS
V
PP
High to Chip Enable Low
2
μ
s
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
2
μ
s
t
ELEH
t
PW
Chip Enable Program Pulse Width
95
105
μ
s
t
EHQX
t
DH
Chip Enable High to Input Transition
2
μ
s
t
QXGL
t
OES
Input Transition to Output Enable Low
2
μ
s
t
GLQV
t
OE
Output Enable Low to Output Valid
100
ns
t
GHQZ
t
DFP
Output Enable High to Output Hi-Z
0
130
ns
t
GHAX
t
AH
Output Enable High to Address
Transition
0
ns
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