參數(shù)資料
型號(hào): M27V102-100B1TR
廠商: 意法半導(dǎo)體
英文描述: 1 Mbit 64Kb x 16 Low Voltage UV EPROM and OTP EPROM
中文描述: 1兆位64Kb的× 16低壓紫外線存儲(chǔ)器和OTP存儲(chǔ)器
文件頁數(shù): 2/15頁
文件大?。?/td> 116K
代理商: M27V102-100B1TR
Q6
Q5
Q4
Q3
Q2
Q11
Q10
Q9
Q8
VSS
Q7
A12
A11
A10
A9
VSS
A8
A7
A6
A5
A4
A3
A13
A2
A1
Q1
Q0
G
A0
NC
A15
P
E
Q12
VPP
VCC
Q15
Q14
Q13
AI01913
M27V102
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
40
39
38
37
36
35
34
33
A14
Figure 2A. DIPPin Connections
AI01914
A
A11
A10
A7
A6
A
23
Q6
Q5
Q4
Q
Q
N
A
Q12
Q11
Q10
Q9
Q8
VSS
NC
Q7
12
A
A9
VSS
NC
A8
1
Q
A12
Q
A5
44
N
N
M27V102
Q
A13
A
34
Q
Q
G
A
A
V
E
P
V
Figure2B. LCC Pin Connections
Warning:
NC = Not Connected.
For application where the content is programmed
only one time and erasure is not required, the
M27V102 is offered in PDIP40, PLCC32 and
TSOP40(10 x 14 mm) packages.
DEVICEOPERATION
The operatingmodes of the M27V102are listedin
theOperating Modes table. Asingle power supply
is required in the read mode. All inputs are TTL
levels exceptfor Vpp and 12V on A9 for Electronic
Signature.
ReadMode
The M27V102 has two control functions, both of
whichmustbelogicallyactiveinorderto obtaindata
attheoutputs. ChipEnable(E)isthepowercontrol
and should be used for device selection. Output
Enable(G) isthe outputcontrolandshouldbe used
to gate data to the output pins, independent of
deviceselection. Assumingthatthe addressesare
stable,the addressaccess time (t
AVQV
) is equal to
thedelayfrom Etooutput(t
ELQV
). Datais available
at the output after a delay of t
OE
from the falling
edge of G, assumingthat E has been low and the
addresses have been stable for at least t
AVQV
-
t
GLQV
.
Warning:
NC = Not Connected.
DQ6
DQ7
VSS
DQ3
DQ4
DQ5
DQ2
DQ13
DQ12
DQ11
DQ8
DQ10
DQ9
A14
A15
NC
A8
A7
A6
A5
A11
A12
A13
A10
A4
A3
A9
G
DQ0
A2
A1
DQ1
A0
P
E
DQ14
VPP
VCC
DQ15
AI01915
M27V102
(Normal)
10
11
1
20
21
30
31
40
VSS
Figure 2C. TSOPPin Connections
Warning:
NC = Not Connected.
DESCRIPTION
(cont’d)
2/15
M27V102
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