參數(shù)資料
型號(hào): M27C4001-90B1
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit (512Kb x 8) UV EPROM and OTP EPROM
中文描述: 4兆位(512KB的× 8)紫外線存儲(chǔ)器和OTP存儲(chǔ)器
文件頁(yè)數(shù): 9/24頁(yè)
文件大?。?/td> 149K
代理商: M27C4001-90B1
M27C4001
Device operation
9/25
2.4
System Considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, I
CC
, has three segments that are of interest to
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1
μ
F ceramic capacitor be used on every device between V
CC
and V
SS
. This should
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7
μ
F bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
2.5
Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C4001 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C4001 is in the programming mode when V
PP
input is at 12.75V, G is at V
IH
and E is
pulsed to V
IL
. The data to be programmed is applied to 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are TTL. V
CC
is specified to be
6.25V ± 0.25V.
2.6
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the whole array to be programmed with a
guaranteed margin, in a typical time of 52.5 seconds. Programming with PRESTO II
consists of applying a sequence of 100
μ
s program pulses to each byte until a correct verify
occurs (see
Figure 5
). During programming and verify operation, a MARGIN MODE circuit is
automatically activated in order to guarantee that each cell is programmed with enough
margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
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