參數(shù)資料
型號: M27C320-100N1
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 4Mb x8 or 2Mb x16 OTP EPROM
中文描述: 32兆位4Mb的x8或檢察官辦公室的2Mb x16存儲器
文件頁數(shù): 3/15頁
文件大?。?/td> 94K
代理商: M27C320-100N1
3/15
M27C320
DEVICE OPERATION
The operatingmodes of the M27C320 are listed in
the Operating Modes Table.A singlepower supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27C320 has two organisations, Word-wide
and Byte-wide.The organisation is selected by the
signal level on the BYTE pin. When BYTE is at V
IH
the Word-wide organisation is selected and the
Q15A–1 pin is used for Q15 Data Output. When
the BYTE pin is at V
IL
the Byte-wide organisation
is selected and the Q15A–1 pin is used for the Ad-
dress Input A–1. When the memory is logically re-
garded as 16 bit wide, but read in the Byte-wide
organisation, then with A–1 at V
IL
the lower 8 bits
of the 16 bit data are selected and with A–1 at V
IH
the upper 8 bits of the 16 bit data are selected.
The M27C320 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.
Chip Enable (E) is thepower control and should be
used for device selection. Output Enable (G)is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C320 has standby mode which reduces
the supply current from 50mA to 100
μ
A. The
M27C320 is placed in the standby mode by apply-
ing aCMOS highsignal to the Einput. Whenin the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.
Table 3. Operating Modes
Note: X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V.
Table 4. Electronic Signature
Note: Outputs Q8-Q15 are set to ’0’.
Mode
E
GV
PP
BYTE
A9
Q0-Q7
Q8-Q14
Q15A–1
Read Word-wide
V
IL
V
IL
V
IH
X
Data Out
Data Out
Data Out
Read Byte-wide Upper
V
IL
V
IL
V
IL
X
Data Out
Hi-Z
V
IH
Read Byte-wide Lower
V
IL
V
IL
V
IL
X
Data Out
Hi-Z
V
IL
Output Disable
V
IL
V
IH
X
X
Hi-Z
Hi-Z
Hi-Z
Program
V
IL
Pulse
V
PP
V
IH
X
Data In
Data In
Data In
Program Inhibit
V
IH
V
PP
V
IH
X
Hi-Z
Hi-Z
Hi-Z
Standby
V
IH
X
X
X
Hi-Z
Hi-Z
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
Codes
Codes
Code
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
0
0
1
1
0
0
1
0
32h
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