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參數(shù)資料
| 型號： | M27C1001-15CTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit (128 Kbit x 8) UV EPROM and OTP EPROM |
| 中文描述： | 1兆位（128千位× 8）紫外線存儲器和OTP存儲器 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 153K |
| 代理商： | M27C1001-15CTR |
M27C1001
Device description
9/24
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
2.4
System considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, I
CC
, has three segments that are of interest to
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1μF ceramic capacitor be used on every device between V
CC
and V
SS
. This should
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7μF bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
2.5
Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C1001 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposition to ultraviolet light (UV EPROM). The
M27C1001 is in the programming mode when V
PP
input is at 12.75V, E is at V
IL
and P is
pulsed to V
IL
. The data to be programmed is applied to 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are TTL. V
CC
is specified to be
6.25V ± 0.25V.
2.6
Presto II programming algorithm
Presto II Programming Algorithm allows the whole array to be programmed, with a
guaranteed margin, in a typical time of 13 seconds. Programming with Presto II involves in
applying a sequence of 100μs program pulses to each byte until a correct verify occurs (see
Figure 5
). During programming and verify operation, a Margin mode circuit is automatically
activated in order to guarantee that each cell is programmed with enough margin. No
overprogram pulse is applied since the verify in Margin mode provides necessary margin to
each programmed cell.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M27C1001-15F1 | 功能描述:可擦除可編程ROM 1M (128Kx8) 150ns RoHS:否 制造商:Maxim Integrated 類型: 存儲容量:1024 bit 組織:1 K x 1 接口類型: 工作電流:5 uA 編程電壓: 工作電源電壓:2.8 V to 6 V 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:TO-92 |
| M27C1001-15F1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
| M27C1001-15F1X | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
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