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參數(shù)資料
| 型號： | M24M01-V |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit Serial IC Bus EEPROM |
| 中文描述： | 1兆位串行IC總線的EEPROM |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 120K |
| 代理商： | M24M01-V |
M24M01
14/19
Table 12. AC Characteristics
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Test conditions specified in Table 7 and Table 5 or Table 6
Symbol
Alt.
Parameter
Min.
Max.
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CH1CH2
t
R
Clock Rise Time
20
300
ns
t
CL1CL2
t
F
Clock Fall Time
20
300
ns
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
DH1DH2 2
t
R
SDA Rise Time
20
300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV 3
t
AA
Clock Low to Next Data Valid (Access Time)
205
900
ns
t
CHDX 1
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start
Condition
1300
ns
t
W
t
WR
Write Time
10
ms
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