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參數(shù)資料
| 型號： | M24C64-WMN6TP |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 9/26頁 |
| 文件大小： | 394K |
| 代理商： | M24C64-WMN6TP |
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M24C64, M24C32
Figure 7. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the Read/Write bit
(RW) reset to 0. The device acknowledges this, as
shown in
Figure 8.
, and waits for two address
bytes. The device responds to each address byte
with an acknowledge bit, and then waits for the
data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
notacknowledged, as shown in
Figure 7.
.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (
Ta-
ble 4.
) is sent first, followed by the Least Signifi-
cant Byte (
Table 5.
). Bits b15 to b0 form the
address of the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal Write cycle is triggered. A Stop
condition at any other time slot does not trigger the
internal Write cycle.
After the Stop condition, the delay t
W
, and the suc-
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
with NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
terminates the transfer by generating a Stop con-
dition, as shown in
Figure 8.
.
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01120C
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
ACK
ACK
NO ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
NO ACK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M24C64BN6T | 18-Bit Universal Bus Transceiver With 3-State Outputs 56-TSSOP -40 to 85 |
| M24C64DW3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64DW5T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64DW6T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C64WBN3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M24C64-WMN6TP/P | 制造商:STMicroelectronics 功能描述:EEPROM SERL-I2C 64KBIT 8KX8 3.3V/5V 8PIN SO N - Tape and Reel |
| M24C64-WMN6TP-CUT TAPE | 制造商:ST 功能描述:M24C64 Series 64 Kb (8 K x 8) 2.5 V SMT Serial I? Bus EEPROM - SOIC-8 |
| M24D16161DA | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| M24D16161DA-70BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| M24D16161ZA | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
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