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參數(shù)資料
| 型號： | M24C16-BN6T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 449K |
| 代理商： | M24C16-BN6T |
3/25
M24C16, M24C08, M24C04, M24C02, M24C01
SUMMARY DESCRIPTION
These I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 2048/1024/512/256/128 x 8 (M24C16,
M24C08, M24C04, M24C02 and M24C01).
In order to meet environmental requirements, ST
offers these devices in ECOPACK packages.
ECOPACK packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 2. Logic Diagram
I2C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I2C bus definition.
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
Table 3.
), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 2. Signal Names
Device internal reset
In order to prevent inadvertent Write operations
during Power-up, a Power On Reset (POR) circuit
is included. At Power-up (continuous rise of V
CC
),
the device will not respond to any instructions until
the V
CC
has reached the Power On Reset
threshold voltage (this threshold is lower than the
V
CC
min. operating voltage defined in
DC and AC
PARAMETERS
). When V
CC
has passed over the
POR threshold, the device is reset and is in
Standby
Power
mode.
(continuous decay of V
CC
), as soon as V
CC
drops
from the normal operating voltage to below the
Power On Reset threshold voltage, the device
stops responding to any instruction sent to it.
Prior to selecting and issuing instructions to the
memory, a valid and stable V
CC
voltage must be
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (t
W
).
At
Power-down
Figure 3. 8-Pin Package Connections (Top View)
Note: 1. NC = Not Connected
2. See
PACKAGE MECHANICAL
section for package dimensions, and how to identify pin-1.
AI02033
3
E0-E2
SDA
VCC
M24Cxx
WC
SCL
VSS
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
SDA
VSS
SCL
WC
VCC
/ E2
AI02034E
M24Cxx
1
2
3
4
8
7
6
5
/ E2
/ E2
/ E2
NC
/ E1
/ E1
/ E1
/ NC
NC
/ E0
/ E0
/ NC
/ NC
NC
/1Kb
/2Kb
/4Kb
/8Kb
16Kb
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M24C16-BN6TG | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16-BN6TP | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16-DS3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16-DS3TG | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16-DS3TP | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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