參數(shù)資料
型號: M24C08-SDW3T
廠商: 意法半導(dǎo)體
元件分類: EEPROM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 18/29頁
文件大小: 483K
代理商: M24C08-SDW3T
M24C16, M24C08, M24C04, M24C02, M24C01
18/29
Table 15. AC Characteristics (M24Cxx, Device Grade 6)
Test conditions specified in
Table 8.
and
Table 5.
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data for M24Cxx-Wxx3.
Table 16. AC Characteristics (M24Cxx, Device Grade 3; M24Cxx-W, Device Grade 6 or 3)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. 10ms write time is offered on the standard device. 5ms write time is offered on new products bearing the Process Identification letter
“W” or “G” on the package, as described in
Table 24.
.
Symbol
Alt.
Parameter
Min.
4
Max.
4
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV 3
t
AA
Clock Low to Next Data Valid (Access Time)
200
900
ns
t
CHDX 1
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition
1300
ns
t
W
t
WR
Write Time
5
ms
Test conditions specified in
Table 8.
and
Table 5.
or
Table 6.
Symbol
Alt.
Parameter
Min.
Max.
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV 3
t
AA
Clock Low to Next Data Valid (Access Time)
200
900
ns
t
CHDX 1
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition
1300
ns
t
W
t
WR
Write Time
10 or
4
5
ms
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M24C64-RMB3TP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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