參數(shù)資料
型號: M24512-WDW6
廠商: 意法半導(dǎo)體
英文描述: CAP 3300UF 50V ELECT SMG RAD
中文描述: 512千位串行I眷總線的EEPROM
文件頁數(shù): 16/24頁
文件大小: 379K
代理商: M24512-WDW6
M24512
16/24
Table 14. AC Characteristics (M24512 – W)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. For M24512 devices whose package marking shows the process letter “A” t
W
(max) = 5ms whereas for M24512 devices whose
package marking shows the process letter “V” t
W
(max) = 10ms
Table 15. AC Characteristics
(1)
(M24512 – R)
Symbol
Alt.
Note: 1. The information contained in
Table 15.
is related to the new M24512 (process letter “A”) and is subject to change without previous
notice.
2. For a reSTART condition, or following a Write cycle.
3. Sampled only, not 100% tested.
4. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Symbol
Alt.
Parameter
Min.
Max.
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
CH1CH2
t
R
Clock Rise Time
300
ns
t
CL1CL2
t
F
Clock Fall Time
300
ns
t
DH1DH2 (2)
t
R
SDA Rise Time
20
300
ns
t
DL1DL2 (2)
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV (3)
t
AA
Clock Low to Next Data Valid (Access Time)
200
900
ns
t
CHDX (1)
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition
1300
ns
t
W
t
WR
Write Time
5 or 10
(4)
ms
Parameter
Min.
Max.
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
DL1DL2 (3)
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV (4)
t
AA
Clock Low to Next Data Valid (Access Time)
200
900
ns
t
CHDX (2)
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition
1300
ns
t
W
t
WR
Write Time
10
ms
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