參數(shù)資料
型號: M24164-WBN1
廠商: 意法半導(dǎo)體
英文描述: 16 Kbit Serial I2C BUS EEPROM
中文描述: 16千位串行I2C總線的EEPROM
文件頁數(shù): 3/21頁
文件大?。?/td> 135K
代理商: M24164-WBN1
3/21
M24164
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con-
nected from Serial Clock (SCL) to V
CC
. (Figure 4
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
. (Fig-
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on three bits (b6, b5, b4) of the
7-bit Device Select Code. These inputs must be
tied to V
CC
or V
SS
, to establish the Device Select
Code.
Write Control (WC)
This input signal is useful for protecting the entire
contents of the memory from inadvertent write op-
erations. Write operations are disabled to the en-
tire memory array when Write Control (WC) is
driven High. When unconnected, the signal is in-
ternally read as V
IL
, and Write operations are al-
lowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 5. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS (pF)
M
)
10
1000
fc = 400kHz
fc = 100kHz
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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