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參數(shù)資料
| 型號(hào)： | M24128 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines |
| 中文描述： | 一百二十八分之二百五十六千位串行IC總線的EEPROM芯片使能線無 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 135K |
| 代理商： | M24128 |
7/17
M24256, M24128
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t
w
) is shown in Table 10, but the
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. Data starts to become over-
written (in a way not formally specified in this data
sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
AI01847C
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YES
NO
START
Condition
Continue the
WRITE Operation
Continue the
Random READ Operation
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相關(guān)代理商/技術(shù)參數(shù) |
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| M24128_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit, 64 Kbit and 32 Kbit serial I2C bus EEPROM |
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| M24128-BF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit, 64 Kbit and 32 Kbit serial IC bus EEPROM |
| M24128-BFBN3/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit, 64 Kbit and 32 Kbit serial I2C bus EEPROM |
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