參數(shù)資料
型號: M24128-MN5T
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines
中文描述: 一百二十八分之二百五十六千位串行IC總線的EEPROM芯片使能線無
文件頁數(shù): 4/17頁
文件大?。?/td> 135K
代理商: M24128-MN5T
M24256, M24128
4/17
must be stable during the clock low-to-high transi-
tion, and the data must change onlywhen the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (0, 0, 0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
The 8
th
bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9
th
bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
Figure 4. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1
2
3
7
8
9
MSB
ACK
START
Condition
SCL
1
2
3
7
8
9
MSB
ACK
STOP
Condition
Table 3. Device Select Code
1
Note: 1. The most significant bit, b7, is sent first.
Device Type Identifier
Chip Enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device Select Code
1
0
1
0
0
0
0
RW
相關(guān)PDF資料
PDF描述
M24128-BN6T 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines
M24128-BN5T 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines
M24164 16 Kbit Serial I2C BUS EEPROM
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