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| 型號(hào)： | M24128-BWMN6TP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Displays |
| 中文描述： | 256Kbit和128Kbit的EEPROM串行I2C總線具有三個(gè)芯片使能線 |
| 文件頁(yè)數(shù)： | 10/17頁(yè) |
| 文件大小： | 135K |
| 代理商： | M24128-BWMN6TP |
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M24256, M24128
10/17
Table 10. AC Characteristics
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Symbol
Alt.
Parameter
M24256 / M24128
Unit
V
CC
=4.5 to 5.5 V
T
A
=–40 to 85°C
V
CC
=2.5 to 5.5 V
T
A
=–40 to 85°C
Min
Max
Min
Max
t
CH1CH2
t
R
Clock Rise Time
300
300
ns
t
CL1CL2
t
F
Clock Fall Time
300
300
ns
t
DH1DH2 2
t
R
SDA Rise Time
20
300
20
300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
20
300
ns
t
CHDX 1
t
SU:STA
Clock High to Input Transition
600
600
ns
t
CHCL
t
HIGH
Clock Pulse Width High
600
600
ns
t
DLCL
t
HD:STA
Input Low to Clock Low (START)
600
600
ns
t
CLDX
t
HD:DAT
Clock Low to Input Transition
0
0
μs
t
CLCH
t
LOW
Clock Pulse Width Low
1.3
1.3
μs
t
DXCX
t
SU:DAT
Input Transition to Clock Transition
100
100
ns
t
CHDH
t
SU:STO
Clock High to Input High (STOP)
600
600
ns
t
DHDL
t
BUF
Input High to Input Low (Bus Free)
1.3
1.3
μs
t
CLQV 3
t
AA
Clock Low to Data Out Valid
200
900
200
900
ns
t
CLQX
t
DH
Data Out Hold Time After Clock Low
200
200
ns
f
C
f
SCL
Clock Frequency
400
400
kHz
t
W
t
WR
Write Time
10
10
ms
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must notacknowledge the last
byte output, and mustgenerate a STOP condition.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
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